The present invention relates to a storage management system and to a microprocessor utilized for this system. More particularly, the invention relates to technology of managing attributes of physical space by using a physical space management table or technology that can be effectively adapted to a multiprocessor system having a logical space management (virtual storage management) system.
The size of a bus is one of the examples of an attribute related to physical space. FIG. 13 illustrates a memory map on physical space wherein most of the memories have a bus size (e.g., the number of bits that can be read or written at one time in parallel) of 32 bits but a ROM has a size of 16 bits and an input/output device (I/O) has a size of 8 bits. A method called dynamic bus sizing has been proposed to realize such a variable bus sizing. According to this method, when a processor makes access to the external bus, a bus controller provided on the external side returns a bus size for the address and the processor executes the processing according to the bus size. Since the data of bus sizes have been set to the external bus controller, access can be made without being brought to consciousness by a program even when the external bus has 16-bit devices and 32-bit devices (memories) in a mixed manner. Thus, the dynamic bus sizing is rich in flexibility in regard to the bus sizing but is not adapted to increasing the speed since the processor determines the address that is to be output in the next bus cycle depending upon the response from the external bus controller. Another example of an attribute related to physical space may be an address pipeline. This is a function which apparently reduces the access time of the memory by outputting a next address before the present bus access is completed. Like dynamic bus sizing, the conventional microprocessor responds to the processor in regard to whether the external bus controller is capable of establishing a pipeline to the address that is designated.
Technology for designating bus sizes at high speeds has been disclosed in, for example, Japanese Patent Laid-Open No. 232062/1987. According to this technology as shown in FIG. 14, a register is provided on a processor to designate a relationship between a physical address and a bus size, so that the bus size can be determined within the processor in response to the physical address. A port width holding register divides the physical address into several regions and holds bus sizes for the regions. The physical address is input to an address discrimination circuit which discriminates to which region it belongs and, then, the corresponding port width holding register reads out bus size data. Depending upon this result, a byte selection controller operates. Thus, the bus size is determined in the processor and the bus access is started making it easy to carry out the operation at high speeds.
Another attribute related to physical space may be reference/change data of physical page in the logical space management. That is, a logical space system including a primary memory accessible with a physical address and the magnetic disc as a secondary memory is corresponding to a page of the secondary memory and, when a page on the logical space does not exist on the primary memory, the page on the secondary memory is copied by an operating system and is executed. In this case, when there is no vacancy in the primary memory, some pages in the primary memory are saved in the secondary memory to provide room for a new page. This procedure takes place in accordance with the reference/change data of physical page. These data are generally prepared in a logic space management table. These data should be managed corresponding to physical space. However, since the logical space management table has been made present already, the data are provided in the logical space management table to make the constitution simple.